1. Field of the Invention
The present invention relates generally to the field of integrated circuits, and particularly Dynamic Random-Access Memories (DRAMs).
2. Description of Related Art
Networking companies are scrambling in a race to design and develop high performance network processing products for the terabit router market while reducing the cost to implement 10 giga-bits per second/OC192 and above optical carrier network interfaces. Terabit routers demand a fatter throughput of data packets for examining an incoming packet, retrieves a next hop location, and transfers the packet to destination. Memory chips serve as integral components in building a fast network infrastructure.
FIG. 1 is a circuit diagram illustrating a conventional parallel test mode circuit diagram. An odd memory cell 11a is coupled between sense amps 11b and sense amps 11c. Signals generated from sense amps 11b and 11c are coupled to a global parallel data bus 11d and a read/write control signal 11e, which further couples to a global parallel input/output (IO) 11f. Similarly, an even memory cell 12a is coupled between sense amps 12b and sense amps 12c. Signals generated from sense amps 12b and 12c are coupled to a global parallel data bus 12d and a read/write control signal 12e, which further couples to a global parallel IO 12f. A main IO 13 couples between global parallel IOs 11e and 12e, and multiple external IOs 14a, 14b, 14c, and 14d. A control circuit 15 receives RAS/CAS/read/write signal 16 and address inputs 17 for activating test signals 18a and 18b or read/write signal 11e and 12e. A shortcoming of this conventional circuit 10 is that there is limited number of IOs, which impose restrictions in expanding and tiling the number of IOs. The conventional circuit 10 also is not able to generate the disturbance test pattern in parallel for testing a neighboring memory cell.
Accordingly, it is desirable to have a DRAM circuit that efficiently performs parallel test of memory cells.